This invention relates generally to analog-to-digital converters and, more particularly, to a successive approximation register (SAR) for an analog-to-digital converter which first counts clock cycles to measure the sampling period and then successively sets the comparison bits.
Successive approximation registers for use in analog-to-digital conversion are well known. Using the successive approximation technique, a plurality of binary weighted bits are successively set and then the corresponding analog level is compared with the analog signal to determine if the binary bit should remain set or be reset. That is, first the most significant bit of a desired binary representation of the analog signal is set. The resulting digital representation (in this case the most significant bit set and the remaining bits reset) is then converted to an analog signal and compared with the original analog input. If the binary representation corresponds to an analog signal which is greater than the original input analog signal, the bit is reset. If the binary representation corresponds to a value which is less, the most significant bit remains set. In either case, the next most significant bit is set and the binary representation (i.e. 0100 . . . 0 or 1100 . . . 0) is converted to an analog signal and compared. In this case, if the binary representation is greater than the original analog input, the next most significant bit is reset. Otherwise, it remains set. This process is repeated until a complete binary representation of the original analog input signal is achieved.
The typical successive approximation register for use in analog-to-digital conversion includes special clock counters to control the sampling period and the successive setting and resetting of the comparison bits. Unfortunately, these counters not only complicate the SAR register but also require additional silicon area in the case of an integrated circuit.